Semiconductor based integrated circuits dies are created from a silicon wafer through the employment of various etching, doping, and depositing steps that are well known in the art. Ultimately, the integrated circuit may be packaged by forming an encapsulant around the integrated circuit so as to form a packaged integrated circuit having a variety of pinouts or mounting and interconnection schemes. Plastic is often utilized as an encapsulant. Integrated circuit packages that utilize plastic as an encapsulant are generally less expensive then other packaging options.
Recently, efforts to improve packaging efficiency has resulted in the use of substrate panels during the packaging process. By way of example, substrate panels are commonly used in grid array and chip scale type packages. FIG. 1A is an illustration of a portion of a panel of integrated circuits 100 including a plurality of integrated circuits 102 mounted to a substrate panel 101. The substrate 101 typically provides both mechanical support for the integrated circuits 102 during the encapsulation procedure as well as electrically conductive paths between each of the plurality of integrated circuits 102 and external circuitry (not shown).
One typical arrangement for encapsulating panel based integrated circuits utilizes a conventional mold 150 as shown in FIG. 1B. The conventional mold may be used to encapsulate a plurality of groups of integrated circuits 102, 103 substantially simultaneously. As shown, a pot 120 feeds molding compound 116 contained within pot 120 to each of a pair of encapsulation regions of 122 and 124 by way of runners exemplified by runners 130 and 140. The portions of substrates 100 and 101 that are needed to facilitate routing of the runners are often effectively wasted, which is a significant concern since the substrate material can be very expensive.
Another typical arrangement for encapsulating panel based integrated circuits utilizes a gang pot mold 155 as shown in FIG. 1C. In this embodiment, molding compound 170 is fed into one or more uniform reservoirs 180 each containing a plurality of integrated circuits 190 mounted upon a substrate panel 192 as well as uniform reservoirs 182 each containing a plurality of integrated circuits 188 mounted upon a substrate 194. Unfortunately, the uniform molding of a plurality of distinct integrated circuits may cause significant warpage of the substrate panel which has an adverse effect on the singulation process. This warpage is due to the stresses induced by the setting molding compound since there is no effective stress relief afforded by the substantially uniform cross sectional area of molding compound 170 covering integrated circuits. Additionally, the uniform molding obscures the locations of each of the plurality of integrated circuits which makes subsequent singulation difficult and time consuming.
In view of the foregoing, it would be desirable to provide more efficient arrangements for encapsulating panels of integrated circuits.